1. Field of Invention
This invention relates to a method and apparatus for achieving a multiple signal impedance control rail for electrically interconnecting a plurality of ultra-thin molded integrated circuit packages stacked to form an ultra-high density three-dimensional module.
2. Discussion of the Related Art
One method of achieving an interconnected ultra high density integrated circuit package comprised of individual integrated circuit packages is to use a rail to interconnect external leads from each of the individual integrated circuit packages in the ultra high density integrated circuit package, or stack. This method is described in parent application Ser. No. 07/561,417, which is incorporated herein by reference.
In applications where the ultra high density integrated circuit stack, or package, comprises dissimilar integrated circuit devices, e.g. memory devices, microprocessor, DMA, etc., there is a need for a signal or enabling signal path that provides various internal interconnections between the individual, dissimilar integrated circuit devices which make up the stack or package, as well as external connections between the package as a whole, or selected individual devices in the stack and external circuitry.
As the number of individual integrated circuit packages which form the package increases, and as operating speeds approach and exceed 100 MHz, the need for impedance control of the packages as a whole and in particular for the external rails becomes critical. With high density stacks operating at 100 MHz, cross-talk between rail elements becomes problematic. Without impedance control, synchronous operation with outside devices is difficult since the impedance on each rail may cause differing amounts of signal delay. Therefore, impedance control of the rails is vital to maintain synchronous operation at high operating frequencies.
The prior art does not provide a method of easily controlling rail impedance. Also, the prior art does not allow multiple signal paths on a single rail or the ability to ground terminate a rail to control the impedance and inter-rail cross-talk.
Packaging techniques for integrated circuits have been developed in the past in an attempt to satisfy demands for miniaturization in the semiconductor industry. Improved methods for miniaturization of integrated circuits enabling the integration of millions of circuit elements into single integrated silicon embodied circuits, or chips, have resulted in increased emphasis on methods to package these circuits in space efficient, yet reliable and mass producible packages.
The introduction of highly sophisticated integrated circuit microprocessors led to the rapid development of complex personal computers and other common bus systems utilizing a variety of integrated circuit elements such as memory devices (DRAMs, SRAMs), programmable logic arrays (PLAs), microprocessors (CPUs), coprocessors, and other related integrated circuit elements which had to be assembled, mounted and interconnected into as compact, yet reliable packages as feasible to satisfy the industry demands for miniaturization.
In contrast to such prior art systems, the packaging method of the present invention provides a reliable, cost efficient, easily manufacturable package with a plurality of ultra thin level-one package elements assembled in an integrated module or level-two package which can be mounted to a printed circuit board directly or via an underlying socket or header. An integral part of the packaging method and apparatus of the present invention provides external rails or conductors having multiple signal path and ground plane elements to provide impedance control and selective interconnectivity among various level-one circuit packages in the level-two module.